Project Information                    d:\proj\ide2lpt\elektor\old\ide2lpt.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 07/19/2001 15:26:17

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

ide2lpt   EPM7064SLC84-10  12       13       16     47      0           73 %

User Pins:                 12       13       16 



Project Information                    d:\proj\ide2lpt\elektor\old\ide2lpt.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Line 3, File d:\proj\ide2lpt\elektor\old\id7.tdf:
   Group MSB will be "A0", overrides default order of bits or BIT0=LSB in Options Statement
Warning: Line 4, File d:\proj\ide2lpt\elektor\old\id7.tdf:
   Group MSB will be "q0", overrides default order of bits or BIT0=LSB in Options Statement
Warning: Line 5, File d:\proj\ide2lpt\elektor\old\reg33.tdf:
   Group MSB will be "d0", overrides default order of bits or BIT0=LSB in Options Statement
Warning: Line 6, File d:\proj\ide2lpt\elektor\old\reg33.tdf:
   Group MSB will be "q0", overrides default order of bits or BIT0=LSB in Options Statement
Warning: Line 5, File d:\proj\ide2lpt\elektor\old\reg34.tdf:
   Group MSB will be "d0", overrides default order of bits or BIT0=LSB in Options Statement
Warning: Line 6, File d:\proj\ide2lpt\elektor\old\reg34.tdf:
   Group MSB will be "q0", overrides default order of bits or BIT0=LSB in Options Statement
Warning: Line 3, File d:\proj\ide2lpt\elektor\old\reg33_6.tdf:
   Group MSB will be "d0", overrides default order of bits or BIT0=LSB in Options Statement
Warning: Line 4, File d:\proj\ide2lpt\elektor\old\reg33_6.tdf:
   Group MSB will be "q0", overrides default order of bits or BIT0=LSB in Options Statement


Project Information                    d:\proj\ide2lpt\elektor\old\ide2lpt.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

ide2lpt@44                        -CS1FX
ide2lpt@45                        -CS3FX
ide2lpt@46                        HA0
ide2lpt@49                        HA1
ide2lpt@48                        HA2
ide2lpt@61                        HD0
ide2lpt@64                        HD1
ide2lpt@67                        HD2
ide2lpt@69                        HD3
ide2lpt@70                        HD4
ide2lpt@74                        HD5
ide2lpt@76                        HD6
ide2lpt@79                        HD7
ide2lpt@80                        HD8
ide2lpt@77                        HD9
ide2lpt@75                        HD10
ide2lpt@73                        HD11
ide2lpt@68                        HD12
ide2lpt@65                        HD13
ide2lpt@63                        HD14
ide2lpt@60                        HD15
ide2lpt@56                        -HRD
ide2lpt@41                        HRESET
ide2lpt@58                        -HWR
ide2lpt@31                        LD0
ide2lpt@29                        LD1
ide2lpt@27                        LD2
ide2lpt@25                        LD3
ide2lpt@24                        LD4
ide2lpt@21                        LD5
ide2lpt@20                        LD6
ide2lpt@17                        LD7
ide2lpt@10                        LI0
ide2lpt@11                        LI1
ide2lpt@16                        LI2
ide2lpt@12                        LI3
ide2lpt@37                        -RCWR
ide2lpt@81                        RESET
ide2lpt@40                        -RHWR
ide2lpt@39                        -RLWR


Project Information                    d:\proj\ide2lpt\elektor\old\ide2lpt.rpt

** FILE HIERARCHY **



|id7:1|
|reg33:3|
|reg33:3|bus_:45|
|reg33:3|bus_:50|
|reg33:3|bus_:55|
|reg33:3|bus_:60|
|reg33:3|bus_:65|
|reg33:3|bus_:70|
|reg33:3|bus_:75|
|reg33:3|bus_:80|
|reg33:2|
|reg33:2|bus_:45|
|reg33:2|bus_:50|
|reg33:2|bus_:55|
|reg33:2|bus_:60|
|reg33:2|bus_:65|
|reg33:2|bus_:70|
|reg33:2|bus_:75|
|reg33:2|bus_:80|
|reg34:8|
|reg34:8|bus_:37|
|reg34:8|bus_:42|
|reg34:8|bus_:47|
|reg34:8|bus_:52|
|reg34:5|
|reg34:5|bus_:37|
|reg34:5|bus_:42|
|reg34:5|bus_:47|
|reg34:5|bus_:52|
|reg34:6|
|reg34:6|bus_:37|
|reg34:6|bus_:42|
|reg34:6|bus_:47|
|reg34:6|bus_:52|
|reg34:7|
|reg34:7|bus_:37|
|reg34:7|bus_:42|
|reg34:7|bus_:47|
|reg34:7|bus_:52|
|reg33_6:54|


Device-Specific Information:           d:\proj\ide2lpt\elektor\old\ide2lpt.rpt
ide2lpt

***** Logic for device 'ide2lpt' compiled without errors.




Device: EPM7064SLC84-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff
    MultiVolt I/O                              = OFF

                    R  R     R  R  R                                         
                    E  E     E  E  E                                         
                    S  S     S  S  S  V                                      
                    E  E     E  E  E  C                 R        V           
                    R  R     R  R  R  C                 E        C        H  
              L  L  V  V  G  V  V  V  I  G  G  G  G  G  S  H  H  C  H  H  D  
              I  I  E  E  N  E  E  E  N  N  N  N  N  N  E  D  D  I  D  D  1  
              1  0  D  D  D  D  D  D  T  D  D  D  D  D  T  8  7  O  9  6  0  
            -----------------------------------------------------------------_ 
          /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
     LI3 | 12                                                              74 | HD5 
   VCCIO | 13                                                              73 | HD11 
    #TDI | 14                                                              72 | GND 
RESERVED | 15                                                              71 | #TDO 
     LI2 | 16                                                              70 | HD4 
     LD7 | 17                                                              69 | HD3 
RESERVED | 18                                                              68 | HD12 
     GND | 19                                                              67 | HD2 
     LD6 | 20                                                              66 | VCCIO 
     LD5 | 21                                                              65 | HD13 
RESERVED | 22                       EPM7064SLC84-10                        64 | HD1 
    #TMS | 23                                                              63 | HD14 
     LD4 | 24                                                              62 | #TCK 
     LD3 | 25                                                              61 | HD0 
   VCCIO | 26                                                              60 | HD15 
     LD2 | 27                                                              59 | GND 
RESERVED | 28                                                              58 | -HWR 
     LD1 | 29                                                              57 | RESERVED 
RESERVED | 30                                                              56 | -HRD 
     LD0 | 31                                                              55 | RESERVED 
     GND | 32                                                              54 | RESERVED 
         |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
           ------------------------------------------------------------------ 
              R  R  R  R  -  V  -  -  H  G  V  -  -  H  G  H  H  R  R  O  V  
              E  E  E  E  R  C  R  R  R  N  C  C  C  A  N  A  A  E  E  E  C  
              S  S  S  S  C  C  L  H  E  D  C  S  S  0  D  2  1  S  S  R  C  
              E  E  E  E  W  I  W  W  S     I  1  3              E  E     I  
              R  R  R  R  R  O  R  R  E     N  F  F              R  R     O  
              V  V  V  V              T     T  X  X              V  V        
              E  E  E  E                                         E  E        
              D  D  D  D                                         D  D        


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:           d:\proj\ide2lpt\elektor\old\ide2lpt.rpt
ide2lpt

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     4/16( 25%)   8/16( 50%)   4/16( 25%)  18/36( 50%) 
B:    LC17 - LC32    12/16( 75%)  10/16( 62%)   0/16(  0%)  25/36( 69%) 
C:    LC33 - LC48    16/16(100%)  11/16( 68%)   0/16(  0%)  29/36( 80%) 
D:    LC49 - LC64    15/16( 93%)  16/16(100%)   0/16(  0%)  25/36( 69%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            45/64     ( 70%)
Total logic cells used:                         47/64     ( 73%)
Total shareable expanders used:                  0/64     (  0%)
Total Turbo logic cells used:                   47/64     ( 73%)
Total shareable expanders not available (n/a):   4/64     (  6%)
Average fan-in:                                  3.53
Total fan-in:                                   166

Total input pins required:                      12
Total fast input logic cells required:           0
Total output pins required:                     13
Total bidirectional pins required:              16
Total reserved pins required                     4
Total logic cells required:                     47
Total flipflops required:                        0
Total product terms required:                  144
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                        18/  64   ( 28%)



Device-Specific Information:           d:\proj\ide2lpt\elektor\old\ide2lpt.rpt
ide2lpt

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  61     47    C      BIDIR               0      0   0    2    1    1    0  HD0
  64     50    D      BIDIR               0      0   0    2    1    1    0  HD1
  67     52    D      BIDIR               0      0   0    2    1    1    0  HD2
  69     54    D      BIDIR               0      0   0    2    1    1    0  HD3
  70     55    D      BIDIR               0      0   0    2    1    1    0  HD4
  74     58    D      BIDIR               0      0   0    2    1    1    0  HD5
  76     60    D      BIDIR               0      0   0    2    1    1    0  HD6
  79     62    D      BIDIR               0      0   0    2    1    1    0  HD7
  80     63    D      BIDIR               0      0   0    2    1    1    0  HD8
  77     61    D      BIDIR               0      0   0    2    1    1    0  HD9
  75     59    D      BIDIR               0      0   0    2    1    1    0  HD10
  73     57    D      BIDIR               0      0   0    2    1    1    0  HD11
  68     53    D      BIDIR               0      0   0    2    1    1    0  HD12
  65     51    D      BIDIR               0      0   0    2    1    1    0  HD13
  63     49    D      BIDIR               0      0   0    2    1    1    0  HD14
  60     46    C      BIDIR               0      0   0    2    1    1    0  HD15
  41   (17)  (B)      INPUT               0      0   0    0    0    1    0  HRESET
  31   (25)  (B)      INPUT               0      0   0    0    0    7    0  LD0
  29   (27)  (B)      INPUT               0      0   0    0    0    7    0  LD1
  27   (29)  (B)      INPUT               0      0   0    0    0    3    0  LD2
  25   (30)  (B)      INPUT               0      0   0    0    0    3    0  LD3
  24   (31)  (B)      INPUT               0      0   0    0    0    3    0  LD4
  21    (2)  (A)      INPUT               0      0   0    0    0    2    1  LD5
  20    (3)  (A)      INPUT               0      0   0    0    0    2    1  LD6
  17    (5)  (A)      INPUT               0      0   0    0    0    2    0  LD7
  37   (20)  (B)      INPUT               0      0   0    0    0    5    2  -RCWR
  40   (18)  (B)      INPUT               0      0   0    0    0    8    0  -RHWR
  39   (19)  (B)      INPUT               0      0   0    0    0    8    0  -RLWR


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:           d:\proj\ide2lpt\elektor\old\ide2lpt.rpt
ide2lpt

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  44     33    C     OUTPUT      t        0      0   0    2    1    3    0  -CS1FX
  45     34    C     OUTPUT      t        0      0   0    2    1    3    0  -CS3FX
  46     35    C     OUTPUT      t        0      0   0    2    1    1    0  HA0
  49     37    C     OUTPUT      t        0      0   0    2    1    1    0  HA1
  48     36    C     OUTPUT      t        0      0   0    2    1    1    0  HA2
  61     47    C        TRI      t        0      0   0    2    1    1    0  HD0
  64     50    D        TRI      t        0      0   0    2    1    1    0  HD1
  67     52    D        TRI      t        0      0   0    2    1    1    0  HD2
  69     54    D        TRI      t        0      0   0    2    1    1    0  HD3
  70     55    D        TRI      t        0      0   0    2    1    1    0  HD4
  74     58    D        TRI      t        0      0   0    2    1    1    0  HD5
  76     60    D        TRI      t        0      0   0    2    1    1    0  HD6
  79     62    D        TRI      t        0      0   0    2    1    1    0  HD7
  80     63    D        TRI      t        0      0   0    2    1    1    0  HD8
  77     61    D        TRI      t        0      0   0    2    1    1    0  HD9
  75     59    D        TRI      t        0      0   0    2    1    1    0  HD10
  73     57    D        TRI      t        0      0   0    2    1    1    0  HD11
  68     53    D        TRI      t        0      0   0    2    1    1    0  HD12
  65     51    D        TRI      t        0      0   0    2    1    1    0  HD13
  63     49    D        TRI      t        0      0   0    2    1    1    0  HD14
  60     46    C        TRI      t        0      0   0    2    1    1    0  HD15
  56     43    C     OUTPUT      t        0      0   0    0    3    1    0  -HRD
  58     45    C     OUTPUT      t        0      0   0    0    3    0    0  -HWR
  10     11    A     OUTPUT      t        1      0   1    2    4    0    0  LI0
  11     10    A     OUTPUT      t        1      0   1    2    4    0    0  LI1
  16      6    A     OUTPUT      t        1      0   1    2    4    0    0  LI2
  12      9    A     OUTPUT      t        1      0   1    2    4    0    0  LI3
  52     40    C     OUTPUT      t        0      0   0    0    2    0    0  OER
  81     64    D     OUTPUT      t        0      0   0    1    0    0    0  RESET


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:           d:\proj\ide2lpt\elektor\old\ide2lpt.rpt
ide2lpt

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (50)    38    C      LCELL    s t        0      0   0    2    1    1   17  |reg33_6:54|~47~1
 (57)    44    C      LCELL    s t        0      0   0    2    1    2    1  |reg33_6:54|~48~1
 (54)    41    C      LCELL    s t        0      0   0    1    2    1    1  |reg34:5|bus_:37|~32~1
 (62)    48    C      LCELL    s t        0      0   0    1    2    1    1  |reg34:5|bus_:42|~32~1
 (51)    39    C      LCELL    s t        0      0   0    1    2    1    1  |reg34:5|bus_:47|~32~1
 (55)    42    C      LCELL    s t        0      0   0    1    2    1    1  |reg34:5|bus_:52|~32~1
 (24)    31    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:6|bus_:37|~32~1
 (31)    25    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:6|bus_:42|~32~1
 (29)    27    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:6|bus_:47|~32~1
 (25)    30    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:6|bus_:52|~32~1
 (41)    17    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:7|bus_:37|~32~1
 (36)    21    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:7|bus_:42|~32~1
 (28)    28    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:7|bus_:47|~32~1
 (30)    26    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:7|bus_:52|~32~1
 (40)    18    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:8|bus_:37|~32~1
 (39)    19    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:8|bus_:42|~32~1
 (37)    20    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:8|bus_:47|~32~1
 (33)    24    B      LCELL    s t        0      0   0    1    2    1    1  |reg34:8|bus_:52|~32~1


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:           d:\proj\ide2lpt\elektor\old\ide2lpt.rpt
ide2lpt

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                 Logic cells placed in LAB 'A'
        +------- LC11 LI0
        | +----- LC10 LI1
        | | +--- LC6 LI2
        | | | +- LC9 LI3
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'A'
LC      | | | | | A B C D |     Logic cells that feed LAB 'A':

Pin
31   -> * * * * | * - * * | <-- LD0
29   -> * * * * | * - * * | <-- LD1
LC41 -> * - - - | * - * - | <-- |reg34:5|bus_:37|~32~1
LC48 -> - * - - | * - * - | <-- |reg34:5|bus_:42|~32~1
LC39 -> - - * - | * - * - | <-- |reg34:5|bus_:47|~32~1
LC42 -> - - - * | * - * - | <-- |reg34:5|bus_:52|~32~1
LC31 -> * - - - | * * - - | <-- |reg34:6|bus_:37|~32~1
LC25 -> - * - - | * * - - | <-- |reg34:6|bus_:42|~32~1
LC27 -> - - * - | * * - - | <-- |reg34:6|bus_:47|~32~1
LC30 -> - - - * | * * - - | <-- |reg34:6|bus_:52|~32~1
LC17 -> * - - - | * * - - | <-- |reg34:7|bus_:37|~32~1
LC21 -> - * - - | * * - - | <-- |reg34:7|bus_:42|~32~1
LC28 -> - - * - | * * - - | <-- |reg34:7|bus_:47|~32~1
LC26 -> - - - * | * * - - | <-- |reg34:7|bus_:52|~32~1
LC18 -> * - - - | * * - - | <-- |reg34:8|bus_:37|~32~1
LC19 -> - * - - | * * - - | <-- |reg34:8|bus_:42|~32~1
LC20 -> - - * - | * * - - | <-- |reg34:8|bus_:47|~32~1
LC24 -> - - - * | * * - - | <-- |reg34:8|bus_:52|~32~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           d:\proj\ide2lpt\elektor\old\ide2lpt.rpt
ide2lpt

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                 Logic cells placed in LAB 'B'
        +----------------------- LC31 |reg34:6|bus_:37|~32~1
        | +--------------------- LC25 |reg34:6|bus_:42|~32~1
        | | +------------------- LC27 |reg34:6|bus_:47|~32~1
        | | | +----------------- LC30 |reg34:6|bus_:52|~32~1
        | | | | +--------------- LC17 |reg34:7|bus_:37|~32~1
        | | | | | +------------- LC21 |reg34:7|bus_:42|~32~1
        | | | | | | +----------- LC28 |reg34:7|bus_:47|~32~1
        | | | | | | | +--------- LC26 |reg34:7|bus_:52|~32~1
        | | | | | | | | +------- LC18 |reg34:8|bus_:37|~32~1
        | | | | | | | | | +----- LC19 |reg34:8|bus_:42|~32~1
        | | | | | | | | | | +--- LC20 |reg34:8|bus_:47|~32~1
        | | | | | | | | | | | +- LC24 |reg34:8|bus_:52|~32~1
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':
LC31 -> * - - - - - - - - - - - | * * - - | <-- |reg34:6|bus_:37|~32~1
LC25 -> - * - - - - - - - - - - | * * - - | <-- |reg34:6|bus_:42|~32~1
LC27 -> - - * - - - - - - - - - | * * - - | <-- |reg34:6|bus_:47|~32~1
LC30 -> - - - * - - - - - - - - | * * - - | <-- |reg34:6|bus_:52|~32~1
LC17 -> - - - - * - - - - - - - | * * - - | <-- |reg34:7|bus_:37|~32~1
LC21 -> - - - - - * - - - - - - | * * - - | <-- |reg34:7|bus_:42|~32~1
LC28 -> - - - - - - * - - - - - | * * - - | <-- |reg34:7|bus_:47|~32~1
LC26 -> - - - - - - - * - - - - | * * - - | <-- |reg34:7|bus_:52|~32~1
LC18 -> - - - - - - - - * - - - | * * - - | <-- |reg34:8|bus_:37|~32~1
LC19 -> - - - - - - - - - * - - | * * - - | <-- |reg34:8|bus_:42|~32~1
LC20 -> - - - - - - - - - - * - | * * - - | <-- |reg34:8|bus_:47|~32~1
LC24 -> - - - - - - - - - - - * | * * - - | <-- |reg34:8|bus_:52|~32~1

Pin
70   -> * - - - - - - - - - - - | - * - - | <-- HD4
74   -> - * - - - - - - - - - - | - * - - | <-- HD5
76   -> - - * - - - - - - - - - | - * - - | <-- HD6
79   -> - - - * - - - - - - - - | - * - - | <-- HD7
80   -> - - - - * - - - - - - - | - * - - | <-- HD8
77   -> - - - - - * - - - - - - | - * - - | <-- HD9
75   -> - - - - - - * - - - - - | - * - - | <-- HD10
73   -> - - - - - - - * - - - - | - * - - | <-- HD11
68   -> - - - - - - - - * - - - | - * - - | <-- HD12
65   -> - - - - - - - - - * - - | - * - - | <-- HD13
63   -> - - - - - - - - - - * - | - * - - | <-- HD14
60   -> - - - - - - - - - - - * | - * - - | <-- HD15
LC38 -> * * * * * * * * * * * * | - * * - | <-- |reg33_6:54|~47~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           d:\proj\ide2lpt\elektor\old\ide2lpt.rpt
ide2lpt

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC33 -CS1FX
        | +----------------------------- LC34 -CS3FX
        | | +--------------------------- LC35 HA0
        | | | +------------------------- LC37 HA1
        | | | | +----------------------- LC36 HA2
        | | | | | +--------------------- LC47 HD0
        | | | | | | +------------------- LC46 HD15
        | | | | | | | +----------------- LC43 -HRD
        | | | | | | | | +--------------- LC45 -HWR
        | | | | | | | | | +------------- LC40 OER
        | | | | | | | | | | +----------- LC38 |reg33_6:54|~47~1
        | | | | | | | | | | | +--------- LC44 |reg33_6:54|~48~1
        | | | | | | | | | | | | +------- LC41 |reg34:5|bus_:37|~32~1
        | | | | | | | | | | | | | +----- LC48 |reg34:5|bus_:42|~32~1
        | | | | | | | | | | | | | | +--- LC39 |reg34:5|bus_:47|~32~1
        | | | | | | | | | | | | | | | +- LC42 |reg34:5|bus_:52|~32~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC33 -> * - - - - - - * * - - - - - - - | - - * - | <-- -CS1FX
LC34 -> - * - - - - - * * - - - - - - - | - - * - | <-- -CS3FX
LC35 -> - - * - - - - - - - - - - - - - | - - * - | <-- HA0
LC37 -> - - - * - - - - - - - - - - - - | - - * - | <-- HA1
LC36 -> - - - - * - - - - - - - - - - - | - - * - | <-- HA2
LC47 -> - - - - - * - - - - - - - - - - | - - * - | <-- HD0
LC46 -> - - - - - - * - - - - - - - - - | - - * - | <-- HD15
LC43 -> - - - - - - - - - * - - - - - - | - - * - | <-- -HRD
LC38 -> - - - - - - - * - - * - * * * * | - * * - | <-- |reg33_6:54|~47~1
LC44 -> - - - - - - - - * * - * - - - - | - - * - | <-- |reg33_6:54|~48~1
LC41 -> - - - - - - - - - - - - * - - - | * - * - | <-- |reg34:5|bus_:37|~32~1
LC48 -> - - - - - - - - - - - - - * - - | * - * - | <-- |reg34:5|bus_:42|~32~1
LC39 -> - - - - - - - - - - - - - - * - | * - * - | <-- |reg34:5|bus_:47|~32~1
LC42 -> - - - - - - - - - - - - - - - * | * - * - | <-- |reg34:5|bus_:52|~32~1

Pin
61   -> - - - - - - - - - - - - * - - - | - - * - | <-- HD0
64   -> - - - - - - - - - - - - - * - - | - - * - | <-- HD1
67   -> - - - - - - - - - - - - - - * - | - - * - | <-- HD2
69   -> - - - - - - - - - - - - - - - * | - - * - | <-- HD3
31   -> - - * - - * - - - - - - - - - - | * - * * | <-- LD0
29   -> - - - * - - - - - - - - - - - - | * - * * | <-- LD1
27   -> - - - - * - - - - - - - - - - - | - - * * | <-- LD2
25   -> - * - - - - - - - - - - - - - - | - - * * | <-- LD3
24   -> * - - - - - - - - - - - - - - - | - - * * | <-- LD4
21   -> - - - - - - - - - - * - - - - - | - - * * | <-- LD5
20   -> - - - - - - - - - - - * - - - - | - - * * | <-- LD6
17   -> - - - - - - * - - - - - - - - - | - - * * | <-- LD7
37   -> * * * * * - - - - - * * - - - - | - - * - | <-- -RCWR
40   -> - - - - - - * - - - - - - - - - | - - * * | <-- -RHWR
39   -> - - - - - * - - - - - - - - - - | - - * * | <-- -RLWR


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           d:\proj\ide2lpt\elektor\old\ide2lpt.rpt
ide2lpt

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                       Logic cells placed in LAB 'D'
        +----------------------------- LC50 HD1
        | +--------------------------- LC52 HD2
        | | +------------------------- LC54 HD3
        | | | +----------------------- LC55 HD4
        | | | | +--------------------- LC58 HD5
        | | | | | +------------------- LC60 HD6
        | | | | | | +----------------- LC62 HD7
        | | | | | | | +--------------- LC63 HD8
        | | | | | | | | +------------- LC61 HD9
        | | | | | | | | | +----------- LC59 HD10
        | | | | | | | | | | +--------- LC57 HD11
        | | | | | | | | | | | +------- LC53 HD12
        | | | | | | | | | | | | +----- LC51 HD13
        | | | | | | | | | | | | | +--- LC49 HD14
        | | | | | | | | | | | | | | +- LC64 RESET
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC50 -> * - - - - - - - - - - - - - - | - - - * | <-- HD1
LC52 -> - * - - - - - - - - - - - - - | - - - * | <-- HD2
LC54 -> - - * - - - - - - - - - - - - | - - - * | <-- HD3
LC55 -> - - - * - - - - - - - - - - - | - - - * | <-- HD4
LC58 -> - - - - * - - - - - - - - - - | - - - * | <-- HD5
LC60 -> - - - - - * - - - - - - - - - | - - - * | <-- HD6
LC62 -> - - - - - - * - - - - - - - - | - - - * | <-- HD7
LC63 -> - - - - - - - * - - - - - - - | - - - * | <-- HD8
LC61 -> - - - - - - - - * - - - - - - | - - - * | <-- HD9
LC59 -> - - - - - - - - - * - - - - - | - - - * | <-- HD10
LC57 -> - - - - - - - - - - * - - - - | - - - * | <-- HD11
LC53 -> - - - - - - - - - - - * - - - | - - - * | <-- HD12
LC51 -> - - - - - - - - - - - - * - - | - - - * | <-- HD13
LC49 -> - - - - - - - - - - - - - * - | - - - * | <-- HD14

Pin
41   -> - - - - - - - - - - - - - - * | - - - * | <-- HRESET
31   -> - - - - - - - * - - - - - - - | * - * * | <-- LD0
29   -> * - - - - - - - * - - - - - - | * - * * | <-- LD1
27   -> - * - - - - - - - * - - - - - | - - * * | <-- LD2
25   -> - - * - - - - - - - * - - - - | - - * * | <-- LD3
24   -> - - - * - - - - - - - * - - - | - - * * | <-- LD4
21   -> - - - - * - - - - - - - * - - | - - * * | <-- LD5
20   -> - - - - - * - - - - - - - * - | - - * * | <-- LD6
17   -> - - - - - - * - - - - - - - - | - - * * | <-- LD7
40   -> - - - - - - - * * * * * * * - | - - * * | <-- -RHWR
39   -> * * * * * * * - - - - - - - - | - - * * | <-- -RLWR


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           d:\proj\ide2lpt\elektor\old\ide2lpt.rpt
ide2lpt

** EQUATIONS **

HRESET   : INPUT;
LD0      : INPUT;
LD1      : INPUT;
LD2      : INPUT;
LD3      : INPUT;
LD4      : INPUT;
LD5      : INPUT;
LD6      : INPUT;
LD7      : INPUT;
-RCWR    : INPUT;
-RHWR    : INPUT;
-RLWR    : INPUT;

-- Node name is 'HA0' = '|reg33_6:54|:42' from file "reg33_6.tdf" line 8, column 7
-- Equation name is 'HA0', type is output 
 HA0     = LCELL( _EQ001 $  GND);
  _EQ001 =  HA0 &  LD0
         #  LD0 &  -RCWR
         #  HA0 & !-RCWR;

-- Node name is 'HA1' = '|reg33_6:54|:43' from file "reg33_6.tdf" line 9, column 7
-- Equation name is 'HA1', type is output 
 HA1     = LCELL( _EQ002 $  GND);
  _EQ002 =  HA1 &  LD1
         #  LD1 &  -RCWR
         #  HA1 & !-RCWR;

-- Node name is 'HA2' = '|reg33_6:54|:44' from file "reg33_6.tdf" line 10, column 7
-- Equation name is 'HA2', type is output 
 HA2     = LCELL( _EQ003 $  GND);
  _EQ003 =  HA2 &  LD2
         #  LD2 &  -RCWR
         #  HA2 & !-RCWR;

-- Node name is 'HD0' = '|reg33:2|bus_:45|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD0', type is bidir 
HD0      = TRI(_LC047, !OER);
_LC047   = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC047 &  LD0
         #  LD0 &  -RLWR
         #  _LC047 & !-RLWR;

-- Node name is 'HD1' = '|reg33:2|bus_:50|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD1', type is bidir 
HD1      = TRI(_LC050, !OER);
_LC050   = LCELL( _EQ005 $  GND);
  _EQ005 =  _LC050 &  LD1
         #  LD1 &  -RLWR
         #  _LC050 & !-RLWR;

-- Node name is 'HD2' = '|reg33:2|bus_:55|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD2', type is bidir 
HD2      = TRI(_LC052, !OER);
_LC052   = LCELL( _EQ006 $  GND);
  _EQ006 =  _LC052 &  LD2
         #  LD2 &  -RLWR
         #  _LC052 & !-RLWR;

-- Node name is 'HD3' = '|reg33:2|bus_:60|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD3', type is bidir 
HD3      = TRI(_LC054, !OER);
_LC054   = LCELL( _EQ007 $  GND);
  _EQ007 =  _LC054 &  LD3
         #  LD3 &  -RLWR
         #  _LC054 & !-RLWR;

-- Node name is 'HD4' = '|reg33:2|bus_:65|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD4', type is bidir 
HD4      = TRI(_LC055, !OER);
_LC055   = LCELL( _EQ008 $  GND);
  _EQ008 =  _LC055 &  LD4
         #  LD4 &  -RLWR
         #  _LC055 & !-RLWR;

-- Node name is 'HD5' = '|reg33:2|bus_:70|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD5', type is bidir 
HD5      = TRI(_LC058, !OER);
_LC058   = LCELL( _EQ009 $  GND);
  _EQ009 =  _LC058 &  LD5
         #  LD5 &  -RLWR
         #  _LC058 & !-RLWR;

-- Node name is 'HD6' = '|reg33:2|bus_:75|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD6', type is bidir 
HD6      = TRI(_LC060, !OER);
_LC060   = LCELL( _EQ010 $  GND);
  _EQ010 =  _LC060 &  LD6
         #  LD6 &  -RLWR
         #  _LC060 & !-RLWR;

-- Node name is 'HD7' = '|reg33:2|bus_:80|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD7', type is bidir 
HD7      = TRI(_LC062, !OER);
_LC062   = LCELL( _EQ011 $  GND);
  _EQ011 =  _LC062 &  LD7
         #  LD7 &  -RLWR
         #  _LC062 & !-RLWR;

-- Node name is 'HD8' = '|reg33:3|bus_:45|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD8', type is bidir 
HD8      = TRI(_LC063, !OER);
_LC063   = LCELL( _EQ012 $  GND);
  _EQ012 =  _LC063 &  LD0
         #  LD0 &  -RHWR
         #  _LC063 & !-RHWR;

-- Node name is 'HD9' = '|reg33:3|bus_:50|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD9', type is bidir 
HD9      = TRI(_LC061, !OER);
_LC061   = LCELL( _EQ013 $  GND);
  _EQ013 =  _LC061 &  LD1
         #  LD1 &  -RHWR
         #  _LC061 & !-RHWR;

-- Node name is 'HD10' = '|reg33:3|bus_:55|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD10', type is bidir 
HD10     = TRI(_LC059, !OER);
_LC059   = LCELL( _EQ014 $  GND);
  _EQ014 =  _LC059 &  LD2
         #  LD2 &  -RHWR
         #  _LC059 & !-RHWR;

-- Node name is 'HD11' = '|reg33:3|bus_:60|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD11', type is bidir 
HD11     = TRI(_LC057, !OER);
_LC057   = LCELL( _EQ015 $  GND);
  _EQ015 =  _LC057 &  LD3
         #  LD3 &  -RHWR
         #  _LC057 & !-RHWR;

-- Node name is 'HD12' = '|reg33:3|bus_:65|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD12', type is bidir 
HD12     = TRI(_LC053, !OER);
_LC053   = LCELL( _EQ016 $  GND);
  _EQ016 =  _LC053 &  LD4
         #  LD4 &  -RHWR
         #  _LC053 & !-RHWR;

-- Node name is 'HD13' = '|reg33:3|bus_:70|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD13', type is bidir 
HD13     = TRI(_LC051, !OER);
_LC051   = LCELL( _EQ017 $  GND);
  _EQ017 =  _LC051 &  LD5
         #  LD5 &  -RHWR
         #  _LC051 & !-RHWR;

-- Node name is 'HD14' = '|reg33:3|bus_:75|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD14', type is bidir 
HD14     = TRI(_LC049, !OER);
_LC049   = LCELL( _EQ018 $  GND);
  _EQ018 =  _LC049 &  LD6
         #  LD6 &  -RHWR
         #  _LC049 & !-RHWR;

-- Node name is 'HD15' = '|reg33:3|bus_:80|:32' from file "bus_.tdf" line 8, column 10
-- Equation name is 'HD15', type is bidir 
HD15     = TRI(_LC046, !OER);
_LC046   = LCELL( _EQ019 $  GND);
  _EQ019 =  _LC046 &  LD7
         #  LD7 &  -RHWR
         #  _LC046 & !-RHWR;

-- Node name is 'LI0' = '|reg34:8|bus_:37|~31~1~3' 
-- Equation name is 'LI0', type is output 
 LI0     = LCELL( _EQ020 $  GND);
  _EQ020 =  _LC017 & !LD0 &  LD1
         #  _LC018 &  LD0 &  LD1
         #  _LC031 &  LD0 & !LD1
         #  _LC041 & !LD0 & !LD1
         #  _LC017 &  _LC018 &  _LC031 &  _LC041;

-- Node name is 'LI1' = '|reg34:8|bus_:42|~31~1~3' 
-- Equation name is 'LI1', type is output 
 LI1     = LCELL( _EQ021 $  GND);
  _EQ021 =  _LC021 & !LD0 &  LD1
         #  _LC019 &  LD0 &  LD1
         #  _LC025 &  LD0 & !LD1
         #  _LC048 & !LD0 & !LD1
         #  _LC019 &  _LC021 &  _LC025 &  _LC048;

-- Node name is 'LI2' = '|reg34:8|bus_:47|~31~1~3' 
-- Equation name is 'LI2', type is output 
 LI2     = LCELL( _EQ022 $  GND);
  _EQ022 =  _LC028 & !LD0 &  LD1
         #  _LC020 &  LD0 &  LD1
         #  _LC027 &  LD0 & !LD1
         #  _LC039 & !LD0 & !LD1
         #  _LC020 &  _LC027 &  _LC028 &  _LC039;

-- Node name is 'LI3' = '|reg34:8|bus_:52|~31~1~3' 
-- Equation name is 'LI3', type is output 
 LI3     = LCELL( _EQ023 $  GND);
  _EQ023 =  _LC026 & !LD0 &  LD1
         #  _LC024 &  LD0 &  LD1
         #  _LC030 &  LD0 & !LD1
         #  _LC042 & !LD0 & !LD1
         #  _LC024 &  _LC026 &  _LC030 &  _LC042;

-- Node name is 'OER' = ':76' 
-- Equation name is 'OER', type is output 
 OER     = LCELL( _EQ024 $  GND);
  _EQ024 = !-HRD
         # !_LC044;

-- Node name is 'RESET' 
-- Equation name is 'RESET', location is LC064, type is output.
 RESET   = LCELL(!HRESET $  GND);

-- Node name is '|reg33_6:54|~47~1' from file "reg33_6.tdf" line 13, column 7
-- Equation name is '_LC038', type is buried 
-- synthesized logic cell 
_LC038   = LCELL( _EQ025 $  GND);
  _EQ025 =  _LC038 &  LD5
         #  LD5 &  -RCWR
         #  _LC038 & !-RCWR;

-- Node name is '|reg33_6:54|~48~1' from file "reg33_6.tdf" line 14, column 7
-- Equation name is '_LC044', type is buried 
-- synthesized logic cell 
_LC044   = LCELL( _EQ026 $  GND);
  _EQ026 =  _LC044 &  LD6
         #  LD6 &  -RCWR
         #  _LC044 & !-RCWR;

-- Node name is '|reg34:5|bus_:37|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC041', type is buried 
-- synthesized logic cell 
_LC041   = LCELL( _EQ027 $  GND);
  _EQ027 =  HD0 &  _LC038
         #  HD0 &  _LC041
         # !_LC038 &  _LC041;

-- Node name is '|reg34:5|bus_:42|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC048', type is buried 
-- synthesized logic cell 
_LC048   = LCELL( _EQ028 $  GND);
  _EQ028 =  HD1 &  _LC038
         #  HD1 &  _LC048
         # !_LC038 &  _LC048;

-- Node name is '|reg34:5|bus_:47|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC039', type is buried 
-- synthesized logic cell 
_LC039   = LCELL( _EQ029 $  GND);
  _EQ029 =  HD2 &  _LC038
         #  HD2 &  _LC039
         # !_LC038 &  _LC039;

-- Node name is '|reg34:5|bus_:52|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC042', type is buried 
-- synthesized logic cell 
_LC042   = LCELL( _EQ030 $  GND);
  _EQ030 =  HD3 &  _LC038
         #  HD3 &  _LC042
         # !_LC038 &  _LC042;

-- Node name is '|reg34:6|bus_:37|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC031', type is buried 
-- synthesized logic cell 
_LC031   = LCELL( _EQ031 $  GND);
  _EQ031 =  HD4 &  _LC038
         #  HD4 &  _LC031
         #  _LC031 & !_LC038;

-- Node name is '|reg34:6|bus_:42|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC025', type is buried 
-- synthesized logic cell 
_LC025   = LCELL( _EQ032 $  GND);
  _EQ032 =  HD5 &  _LC038
         #  HD5 &  _LC025
         #  _LC025 & !_LC038;

-- Node name is '|reg34:6|bus_:47|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC027', type is buried 
-- synthesized logic cell 
_LC027   = LCELL( _EQ033 $  GND);
  _EQ033 =  HD6 &  _LC038
         #  HD6 &  _LC027
         #  _LC027 & !_LC038;

-- Node name is '|reg34:6|bus_:52|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC030', type is buried 
-- synthesized logic cell 
_LC030   = LCELL( _EQ034 $  GND);
  _EQ034 =  HD7 &  _LC038
         #  HD7 &  _LC030
         #  _LC030 & !_LC038;

-- Node name is '|reg34:7|bus_:37|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC017', type is buried 
-- synthesized logic cell 
_LC017   = LCELL( _EQ035 $  GND);
  _EQ035 =  HD8 &  _LC038
         #  HD8 &  _LC017
         #  _LC017 & !_LC038;

-- Node name is '|reg34:7|bus_:42|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC021', type is buried 
-- synthesized logic cell 
_LC021   = LCELL( _EQ036 $  GND);
  _EQ036 =  HD9 &  _LC038
         #  HD9 &  _LC021
         #  _LC021 & !_LC038;

-- Node name is '|reg34:7|bus_:47|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC028', type is buried 
-- synthesized logic cell 
_LC028   = LCELL( _EQ037 $  GND);
  _EQ037 =  HD10 &  _LC038
         #  HD10 &  _LC028
         #  _LC028 & !_LC038;

-- Node name is '|reg34:7|bus_:52|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC026', type is buried 
-- synthesized logic cell 
_LC026   = LCELL( _EQ038 $  GND);
  _EQ038 =  HD11 &  _LC038
         #  HD11 &  _LC026
         #  _LC026 & !_LC038;

-- Node name is '|reg34:8|bus_:37|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC018', type is buried 
-- synthesized logic cell 
_LC018   = LCELL( _EQ039 $  GND);
  _EQ039 =  HD12 &  _LC038
         #  HD12 &  _LC018
         #  _LC018 & !_LC038;

-- Node name is '|reg34:8|bus_:42|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC019', type is buried 
-- synthesized logic cell 
_LC019   = LCELL( _EQ040 $  GND);
  _EQ040 =  HD13 &  _LC038
         #  HD13 &  _LC019
         #  _LC019 & !_LC038;

-- Node name is '|reg34:8|bus_:47|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC020', type is buried 
-- synthesized logic cell 
_LC020   = LCELL( _EQ041 $  GND);
  _EQ041 =  HD14 &  _LC038
         #  HD14 &  _LC020
         #  _LC020 & !_LC038;

-- Node name is '|reg34:8|bus_:52|~32~1' from file "bus_.tdf" line 8, column 10
-- Equation name is '_LC024', type is buried 
-- synthesized logic cell 
_LC024   = LCELL( _EQ042 $  GND);
  _EQ042 =  HD15 &  _LC038
         #  HD15 &  _LC024
         #  _LC024 & !_LC038;

-- Node name is '-CS1FX' = '|reg33_6:54|:46' from file "reg33_6.tdf" line 12, column 7
-- Equation name is '-CS1FX', type is output 
 -CS1FX  = LCELL( _EQ043 $  GND);
  _EQ043 =  -CS1FX &  LD4
         #  LD4 &  -RCWR
         #  -CS1FX & !-RCWR;

-- Node name is '-CS3FX' = '|reg33_6:54|:45' from file "reg33_6.tdf" line 11, column 7
-- Equation name is '-CS3FX', type is output 
 -CS3FX  = LCELL( _EQ044 $  GND);
  _EQ044 =  -CS3FX &  LD3
         #  LD3 &  -RCWR
         #  -CS3FX & !-RCWR;

-- Node name is '-HRD' = ':75' 
-- Equation name is '-HRD', type is output 
 -HRD    = LCELL( _EQ045 $  GND);
  _EQ045 =  -CS1FX &  -CS3FX
         # !_LC038;

-- Node name is '-HWR' = ':74' 
-- Equation name is '-HWR', type is output 
 -HWR    = LCELL( _EQ046 $  GND);
  _EQ046 =  -CS1FX &  -CS3FX
         # !_LC044;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                    d:\proj\ide2lpt\elektor\old\ide2lpt.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = FAST

      Logic option settings in 'FAST' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = off
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = off
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = off
      Automatic Global Clear              = off
      Automatic Global Preset             = off
      Automatic Global Output Enable      = off
      Automatic Fast I/O                  = on
      Automatic Register Packing          = on
      Automatic Open-Drain Pins           = off
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 10

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:03
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,564K
